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IEEE Based 2016 - 2017 VLSI Projects

S.NO List Of Domains Index
1 FinFETs 1-10
2 Low Power VLSI CMOS Design 11-25
3 Data Security 26-40
4 Digital Circuits 41-56
5 Filters 57-67
6 Communication 68-87
7 Reversible Logic 88-102
8 FPGA Implementation Using MATLAB System generator 103-111
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  1. SRAM stability design comprehending 14nm FinFET Reliability
  2. Performance Evaluation of Optimized Transistor Networks Built Using Independent-Gate FinFET
  3. Parasitic Gate Resistance Impact on Triple-Gate FinFET CMOS Inverter
  4. Low Voltage, High Speed FinFET Based I-BIT BBL-PT Full Adders
  5. Hierarchical Design of Robust and Low Data Dependent FinFET Based SRAM Array
  6. Design of FinFET based All-Digital DLL for Multiphase Clock Generation
  7. Circuit and Architectural Co-Design for Reliable Adder Cells With Steep Slope Tunnel Transistors for Energy Efficient Computing
  8. Calculation of Average Power, Leakage power, and leakage Current of FinFET based 4-bit Priority Encoder
  9. 14nm FinFET Based Supply Voltage Boosting Techniques for Extreme Low Vmin Operation
  10. A 0.6V 1.5GHz 84Mb SRAM Design in 14nm FinFET CMOS Technology
  11. Low Power VLSI CMOS Design

  12. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
  13. A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory.
  14. Design and Implementation of 15-4 Compressor Using I-bit Semi Domino Full Adder at 28nm Technology
  15. Design and Implementation of Arithmetic Logic Unit (ALU) using Modified Novel Bit Adder in QCA
  16. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
  17. High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation
  18. Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier
  19. An Efficient Timing Analysis Model for 6T FinFET SRAM using Current-Based Method
  20. Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS.
  21. Design of High- speed Power efficient full adder with Body-biasing.
  22. Full-Swing Local Bit line SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
  23. Design of a Low Power 4x4 Multiplier Based on Five Transistors (5-T) Half Adder, Eight Transistor (8-T) Full Adder & Two Transistor (2-T) AND Gate
  24. Design and Implementation Of ERSFQ Based GDI Technique Using Tanner
  25. Design Of Extended 4-Bit Full Adder Circuit
  26. Customizable logic cell design using variable body bias
  27. Data Security

  28. Implementation of AES Algorithm to Over Fake Keys against Counter Attacks
  29. Low Delay AES Polynomial Basis Multiplier
  30. A High Efficient Fault Attack On AES S-BOX
  31. An Efficient Implementation Of a Fully Combinational Pipelined S-Box On FPGA
  32. A VLSI Architecture for Security Based Steganographic Processor with AES Algorithm
  33. VLSI Implementation of High Performance Montgomery Modular Multiplication for Crypto graphical Application
  34. New Architecture Of Low Area AES S-BOX/Inv S-BOX Using VLSI Implementation
  35. High Speed Architecture Implementation of AES using FPGA
  36. Design and Implementation of Low Power AES Based Crypto-Processor
  37. Design and Implementation of Low Area S-Box for AES Algorithm
  38. Analysis of the Effective Advanced Encryption Standard Algorithm
  39. Area & Power Optimization Of AES Algorithm Using Modified Mix column With Composite S-Box
  40. Multiplexer based High Throughput S-box for AES Application
  41. Design and Optimization of AES-CM with Composite Field S-Box Architecture
  42. Design of a High Speed and Area Efficient Optimized Mix column for AES
  43. Digital Circuits

  44. Design of Low power and Area efficient Digital FIR filter using Modified MAC unit
  45. Design of Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder
  46. Design of Low Power Wallace Multiplier using Modified Full Adder Circuit
  47. Design of Ultra Low Power Multipliers using Hybrid Adders
  48. Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder
  49. Design of High speed Vedic Multiplier using multiplexer based adder
  50. Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier
  51. Implementation of A High Speed Multiplier for High-Performance and Low Power Applications
  52. Design and performance analysis of a High speed MAC using different multipliers
  53. Design of Area and Power Efficient Digital FIR Filter Using Modified MAC Unit
  54. High Performance VLSI Adders
  55. Design of Carry Select Adder for Low-Power and High Speed VLSI Applications
  56. VLSI Implementation of an improved multiplier for FFT Computation in Biomedical Applications
  57. High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
  58. FPGA Implementation of Scalable Micro programmed FIR Filter Architectures using Wallace Tree and Vedic Multipliers
  59. Low power compressor based MAC architecture for DSP applications
  60. Filters

  61. Area Efficient Re472loadable FIR Filter based on NEw Distributed Arithmetic (NEDA)
  62. MAC Unit for Reconfigurable Systems Using Multi-Operand Adders with Double Carry-Save Encoding
  63. Hardware Implementation Of FIR/IIR Digital Filters Using Integral Stochastic Computation
  64. FIR Filter Design using Multiple Constant Multiplication (MCM) Method with Modified Ripple Carry Adder
  65. Implementation and Impact of LNS MAC Units in Digital Filter Application
  66. Design and FPGA Implementation of Sequential Digital FIR Filter using Micro programmed Controller
  67. Efficient Implementation of Multiplier for Digital FIR Filters
  68. High Speed Multiplication and Accumulation (MAC) Design for Digital Fir Filter
  69. FPGA based Architectures for High Performance Adaptive FIR Filter Systems
  70. Design of Optimized Low Power and Area Efficient Digital FIR Filter using Modified Group Structures based Square Root Carry Select Adder
  71. Design and Implementation of a Novel High Performance Digital FIR Filter for DSP application
  72. Communication

  73. Design of Optimized bit parallel multiplier based 32-point mixed R2SDF R4MDC FFT Architecture
  74. Simulation of 32-point Split Radix multipath delay commutator (SRMDC) based FFT Architecture
  75. Area Efficient 64-point Split Radix FFT using single path delay feedback and multipath delay commutator (SDF-MDC) Architecture
  76. VLSI based pipelined Architecture design for Radix-8 combined SDF-SDC FFT
  77. A Novel VLSI based pipelined Radix-4 Single path delay commutator (R4SDC) FFT
  78. Design of single error correction Double Adjacent error detection triple adjacent error detection- Tetra adjacent error detection (SEC-DAED-TAED-TETRA-AED) Codes
  79. Design of Optimized Complex Multiplier for R2MDC FFT
  80. Area and Delay Minimization of Radix-2k Feed forward FFT Architecture
  81. Complex-Multiplier Implementation for Pipelined FFTs in FPGAs
  82. VLSI Based Adaptive FFT Model for OFDM Application
  83. A Novel Pipelined Radix2-64 Point FFT with Modified Complex Multiplier in OFDM for Wireless Ad hoc Networks
  84. Efficient Implementation of AOFDM with help of Modified R2MDC FFT
  85. VLSI Based Adaptive Modulation and Adaptive OFDM
  86. Efficient VLSI implementation of FFT for orthogonal frequency division multiplexing applications
  87. FPGA Implementation Of Reconfigurable FFT Architecture
  88. A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications
  89. A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
  90. Constant twiddle factor multiplier sharing in multipath delay feedback parallel pipelined FFT processors
  91. Implementation Of 128 Point FFT Processor Using R2SDF Architecture
  92. Parallel Extensions to Single-Path Delay-Feedback FFT Architectures
  93. Reversible Logic

  94. Design of Low Power Multiplier for High Speed DSP application
  95. Design of a Power Optimized FIR filter for speech signal processing
  96. A 32 Bit MAC Unit Design Using Vedic Multiplier and Reversible Logic Gate
  97. Design and implementation of Reversible Central processing Unit
  98. Low Power Reversible Wallace Tree Multiplier Design
  99. Optimized Design of Full-Subtractor Using New SRG Reversible Logic Gates and Verilog HDL Simulation
  100. Design and Implementation Of Hardware Efficient Multiplier: Reversible Logic Gate Approach for Low power
  101. Implementation of a High Speed Multiplier for High-Performance and Low Power Applications
  102. A Novel Reversible Combinational Circuit Design for Low Power Computation
  103. Design of Compact and Low Power Reversible Comparator
  104. Design of Optimized Reversible Binary adders and Multipliers
  105. Implementation of Digital Circuits using Reversible Logic
  106. Parity Preserving Adder/Subtractor using a Novel Reversible Logic Approach
  107. An Improved Design of a Reversible Fault Tolerant LUT-Based System
  108. Design of Optimized Reversible Binary and BCD Adders
  109. FPGA Implementation Using MATLAB System Generator

  110. Design and Implementation of Floating Point Arithmetic Operation Using System Generator
  111. Design and Implementation of Normal Arithmetic Operations Using System Generator
  112. Design and Implementation of Low Power and Area Efficient Bi-Recoder Multiplier
  113. Design And Implementation Of Fast Floating Point Multiplier Unit
  114. Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder
  115. Design of Area and Power Aware Reduced Complexity Wallace Tree Multiplier Implementation of A High Speed Multiplier for High-Performance and Low Power Application
  116. Design and FPGA Implementation of Optimized 32-Bit Vedic Multiplier and Square Architectures
  117. Design of Carry Select Adder for Low-Power and High Speed VLSI Applications
  118. Area?Delay?Power Efficient Carry-Select Adder

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